Ah new reading for the morning coffee...
nferences
22FDX Technology Receives Warm Reception at Major Conferences
- By: Gary Dagastine
- July 7, 2017
The World’s First 2Xnm embedded MRAM for GP-MCU, and an Overview of mmWave Capabilities for 5G Applications, Generate Strong Interest
22FDX® technology created quite a stir when it took the stage at two major international conferences recently, which shows that it is opening up new horizons for customers in today’s fastest-growing semiconductor markets.
At the VLSI Technology Symposium in Kyoto, Japan, some 500 people listened to GF Fellow Danny Shum describe a 22FDX manufacturing breakthrough in embedded STT-MRAM non-volatile memory (eMRAM). In fact, following his talk the audience continued to pepper him with questions as the five-minute Q&A time ran out and throughout the subsequent 20-minute break before the next session. They covered the waterfront, from questions about specific technical details like the material stack, process technology, test results and tooling; to broader issues including product roadmap, business strategy, partnership opportunities and PDK availability.
This strong interest stems from the view that eMRAM technology promises to displace the eFlash NVM now used for code storage and working memory in general-purpose microcontrollers and IoT devices, which are in high demand. GF, with its partner Everspin Technologies, demonstrated the capability to use eMRAM in applications requiring high reliability in harsh environments, such as automotive SoCs.
The full VLSI paper, CMOS-embedded STT-MRAM Arrays in 2x nm Nodes for GPMCU applications, is available for download on the GF website.
Meanwhile, at the IEEE International Microwave Symposium in Honolulu, Hawaii, GF Senior Fellow and RF Chief Technical Officer David Harame outlined the benefits of partially and fully depleted SOI technology (the basis for 22FDX) for RF millimeter wave (mmWave) applications in forthcoming 5G devices. His talk was part of a workshop session he and GF colleagues Ned Cahoon, Baljit Chandhoke and Anirban Bandyopadhyay organized on how silicon technologies and especially 22FDX are now ripe for deployment in mmWave applications versus older, more specialized and costlier technologies.
Together, the talks illustrate the versatility of 22FDX for an ever-expanding range of uses in automotive, mobility/RF connectivity, Internet of Things (IoT), networking and other applications.
Commentary- seems to fit S Johnson's adjacent possible?
Embedded STT-MRAM
An increasing number of applications now require chips that contain embedded non-volatile memory (eNVM), but as devices scale smaller and low-power operation becomes ever more critically important, traditional eFlash NVM is increasingly challenged. That’s because of its relatively high voltage requirements and the difficulty in scaling a key component – its tunnel oxide – without comprising performance and reliability.
A number of alternative eNVM technologies exist, but while eMRAM has long been seen as potentially offering the best combination of scalability, write speed, memory retention, long-term reliability and low-power operation, until now no commercially viable high-density STT-MRAM embedded memory array had ever been demonstrated.
That is, not until Shum announced one at the VLSI conference. He described how GF in collaboration with Everspin Technologies built and demonstrated the world’s first 40Mb CMOS array with an integrated eMRAM at 2x-nm design rules.
A key attribute is its ability to withstand temperatures of 260ºC for at least five minutes, meaning that the typical solder reflow steps required for packaging and final assembly will not change the memory contents, and that code storage can be performed during wafer probe. In addition, the GF 22FDX eMRAM is designed to retain data for more than 10 years at 150°C, which allows the technology to be considered for use in automotive SoCs.
Other important features are that the memory is fabricated at the back-end-of-the-line (BEOL) so that sensitive logic devices and circuitry aren’t damaged during high-temperature front-end-of-the-line (FEOL) process steps. This also enables reusable IP because the same PDK is used. The memory array also runs off the chip’s core voltage power supply (Vdd and I/O), with no need to charge-pump the voltage.
GLOBALFOUNDRIES will offer eMRAM technology as part of its overall 22FDX portfolio of solutions next year, and will begin customer prototyping on multi-project wafers (MPWs) late this year.
22FDX Silicon for mmWave
At the Microwave Symposium, Harame described how the market for high volumes of silicon-based chips operating at mmWave frequencies is blossoming because of the move to 5G wireless standards. (See also, Executive Perspective: Everything’s Going Wireless, And RF Chips Are Enabling It)
He explained how partially and fully depleted SOI technology (PDSOI and FDX, respectively) is a cost-effective silicon-based platform well-suited for these uses because it features low transistor leakage current (e.g., low parasitics).
Already, he noted, there is a broad base of experience with SOI technology because cellular and Wi-Fi switches are widely built using SOI technologies at older technology nodes. One example is 45nm PDSOI, which also has been investigated for many mmWave phased-array system applications. That’s because the ability to stack transistors in PDSOI greatly increases power-handling capabilities even as it enables switches and power amplifiers to be built using low voltage CMOS devices.
His talk focused on how FDX extends such performance to even higher levels because of its high-k dielectric/metal gate stack (high-k/MG), 22nm gate length, and thin silicon channel, which all combine to make it well-suited for forthcoming 5G mmWave applications.
Saturday, July 8, 2017
Friday, July 7, 2017
Slide 25 of China deck..
one phrase
We are uniquely positioned to leverage nearly 30 years of FPGA technology and product investment into our new licensing model
Commentary; The extra time reading in depth was so useful. 22FDX as a model is so good. Well thought out, yrs in the making, a very, very good fit for IoT use. Billions plunked down on the table for Dresden. Recent dots of players signing on and that 22 is gaining strength.
Add in that snip from the QUIK job of Jan.....
ArcticPro eFPGA is being licensed by several Tier-1 customers for integration into their SoCs.
+
S Johnsons work on adjacent possible...... a few snips of text
For me, the most important message in Steven’s article is the notion of the “adjacent possible.” I can’t describe it more eloquently than Steven, so I’ll just let him:
The adjacent possible is a kind of shadow future, hovering on the edges of the present state of things, a map of all the ways in which the present can reinvent itself.
As Steven notes, the adjacent possible “captures both the limits and the creative potential of change and innovation.”
It’s the ever-present set of opportunities at the boundaries of our reach. And:
The strange and beautiful truth about the adjacent possible is that its boundaries grow as you explore them. Each new combination opens up the possibility of other new combinations.
Great leaps beyond the adjacent possible are rare and doomed to be short-term failures. The environment is simply not ready for them yet.
What have I learned that has affected my own subjective probabilities?
I understand now why Dr Saxe said that- 22 being a very good node.
That there is real reason for the boldface type on slide 25.
This IP initiative is fantastic as the limits placed on this small company are gone.
What does this have to do with QUIK? is gone as a question.
So the adjacent possible for QUIK has grown an order of magnitude or more...its what ALL the Tier 1 SOC/ASIC makers
have for their adjacent possibles. The value of such IP has also gone up a multiple of the current market cap is what the Adjacent possible has to say.
I can feel that the scale of this is more than I had considered 6 mo ago.
Always keep something to look forward to...and now
I can't wait to read a Soc name.
Wednesday, July 5, 2017
For QUIK fans it can be hard to wait for new news item to sink into...for me I am having a blast reading the Glo FO Blogs.
Yes the most recent has Dr. Saxe's nice item, but there are so many other interesting one there...
https://blog.globalfoundries.com/meet-mark-granger-gfs-new-vp-automotive-product-line-management/
Meet Mark Granger, GF’s New VP of Automotive Product Line Management
The ADAS space has particularly challenging requirements for energy efficiency and cost, and 22FDX enables unique and compelling solutions. It has already drawn great interest for SoCs for use in forward-view cameras for automated emergency braking systems and automated highway driving. One example is Dream Chip Technologies’ 22FDX-based SoC for automotive computer vision applications. It supports high-end computer-vision performance at very low power consumption, which enables ADAS functions such as road-sign recognition, lane-departure warning, driver-distraction warning, blind spot detection, surround vision, parking assist, pedestrian detection, cruise control and emergency braking.
The other big market for 22FDX technology is microcontrollers, where we bring best-in-class solutions. High-end cars may contain up to ~100 microcontrollers to manage the engine, transmission, powertrain, safety systems, etc.,
I had no idea it was sooooo Many/car..
and that number is going to increase but also drive demand for integration of multiple functions on a single MCU – ideal for 22FDX.
It’s a very exciting time to be involved in this industry, both from business and human perspectives.
So if you are a fan of QUIK eFPGA at 22 then take a few minutes each and every day to read a bog item.
5 star fun.
Commentary..
We have this important snip of text from the QUIK Jan job opening...
ArcticPro eFPGA is being licensed by several Tier-1 customers for integration into their SoCs.
So the reading is not a waste of time as it will provide background. Tier 1 makers of SoCs.
Back in Jan it was NOT just the Fab, it was Tier 1 maker of SoCs.
Can't wait to read a name or two. How much of that is priced in?
Zippo( IMO
Yes the most recent has Dr. Saxe's nice item, but there are so many other interesting one there...
https://blog.globalfoundries.com/meet-mark-granger-gfs-new-vp-automotive-product-line-management/
Meet Mark Granger, GF’s New VP of Automotive Product Line Management
- By: Communications
- May 15, 2017
- What differentiates GF and puts us in a strong position to take advantage of this tremendous opportunity?
The ADAS space has particularly challenging requirements for energy efficiency and cost, and 22FDX enables unique and compelling solutions. It has already drawn great interest for SoCs for use in forward-view cameras for automated emergency braking systems and automated highway driving. One example is Dream Chip Technologies’ 22FDX-based SoC for automotive computer vision applications. It supports high-end computer-vision performance at very low power consumption, which enables ADAS functions such as road-sign recognition, lane-departure warning, driver-distraction warning, blind spot detection, surround vision, parking assist, pedestrian detection, cruise control and emergency braking.
The other big market for 22FDX technology is microcontrollers, where we bring best-in-class solutions. High-end cars may contain up to ~100 microcontrollers to manage the engine, transmission, powertrain, safety systems, etc.,
I had no idea it was sooooo Many/car..
and that number is going to increase but also drive demand for integration of multiple functions on a single MCU – ideal for 22FDX.
- Any other thoughts you’d like to share?
It’s a very exciting time to be involved in this industry, both from business and human perspectives.
So if you are a fan of QUIK eFPGA at 22 then take a few minutes each and every day to read a bog item.
5 star fun.
Commentary..
We have this important snip of text from the QUIK Jan job opening...
ArcticPro eFPGA is being licensed by several Tier-1 customers for integration into their SoCs.
So the reading is not a waste of time as it will provide background. Tier 1 makers of SoCs.
Back in Jan it was NOT just the Fab, it was Tier 1 maker of SoCs.
Can't wait to read a name or two. How much of that is priced in?
Zippo( IMO
Sunday, July 2, 2017
Inside FD-SOI And Scaling
MARK LAPEDUS
![[IMG]](https://semiengineering.com/wp-content/themes/se_current/images/pop_ratings/pop_rating_lev4.png)
Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation.
SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI in R&D. Why develop both finFETs and FD-SOI?
Patton: We are providing our customers with technology that’s really optimized for their applications. We are not trying to fit everybody from high-end servers to battery-powered devices into one technology flavor.
SE: There is some confusion where FD-SOI and finFETs compete in the market. Can you elaborate?
Patton: I am a big fan of finFETs. I spend a lot of my time on 7nm. We are trying to get that ready for customer tape-outs early next year. It’s a great technology if you are used on performance. If you are making large chips and you have a lot of wire capacitance, you love the drive current of a finFET device. But if you are making smaller chips, where the gate capacitance is a bigger issue, then the finFET has a little bit of a disadvantage. Also, it’s a much more complex process. Not everybody is making a million wafers for their products. It’s a more expensive process. And it has more complexity with double-, triple- and quadruple- pattering, as well as the complexities with RF and analog design in a finFET device.
SE: What about FD-SOI?
Patton: FD-SOI is really a technology optimized for the low-cost IoT, battery-powered, low-end mobile and automotive applications.
SE: Do you push one technology over another?
Patton: We’re agnostic. We’re not telling customers that you have to do finFETs or FD-SOI. We want customers to use the technology that fits their application.
SE: Who are the early adopters for 22nm FD-SOI?
Patton: Automotive is definitely one of the strong ones. The camera space is another, and some of the battery-powered IoT.
SE: What’s happening in automotive?
Patton: Certain applications in automotive are better optimized for FD-SOI like radar. Other applications may use finFETs. So we are actually going through automotive qualification in our Malta fab for 14nm. Again, the auto makers can choose.
SE: GlobalFoundries has announced 22nm FD-SOI with plans to add more capabilities to the technology, right?
Patton: The base technology is done. The base IP development is done. And now, we are working on the extensions. We believe one of the killer applications for this is to be able to do a single-chip solution for the IoT space. That’s RF and everything.
SE: What else are you doing with FD-SOI?
Patton: There’s embedded memory. We have MRAM, which we will bring in. And, of course, we have 12nm work going on.
SE: IP is key for FD-SOI, right?
Patton: The yields are basically at 28nm yields. Performance is above our targets. It’s fully qualified. Now the focus is continuing to build up the IP ecosystem. We have the foundation and application IP in place.
SE: 22nm is one of the new battlegrounds in the foundry business. First, GlobalFoundries rolled out 22nm FD-SOI. Then, TSMC introduced a 22nm bulk process. And Intel introduced a new version of its 22nm finFET technology. What’s happening here? And how does 22nm FD-SOI stack up against the other technologies?
Patton: All of a sudden, 22nm has become a big battleground. Certainly, if you are looking at anything with RF requirements, I wouldn’t even put finFET in the game, because finFETs don’t have the same RF capabilities that a planar device has. So it becomes bulk versus FD-SOI. And FD-SOI is really optimized for this low-power space. With bulk, you don’t have the ability to do body-bias.
![[IMG]](https://semiengineering.com/wp-content/uploads/2017/06/bulkvsfdsoi.png)
Fig. 1: Bulk CMOS vs FD-SOI. Source: GlobalFoundries
![[IMG]](https://semiengineering.com/wp-content/uploads/2017/06/Fig.2.png)
Fig. 2: 7nm finFET. Source: GlobalFoundries
SE: There is a perception that only a few customers have adopted FD-SOI. What are the challenges of getting more adoption for FD-SOI?
Patton: We’ve worked with lead customers on FD-SOI and they now understand the issues. First, there was the history or concerns about execution. We are well past that.
Commentary: This is important...with there Dresden news of FDX a PILLAR with China Chengdu center of excellence.....there are huge news items to show how well FDX is rolling along now
People understand 22nm. It’s solid technology and it’s yielding very well. We’ve executed what we’ve planned. We knew IP was going to be critical, because FD-SOI is new and different for people. So we’ve been investing from the beginning on the IP ecosystem. Our initial partner was Invecas to help build up the foundational IP. Since then, we’ve made a big increase and investment in all of the IP around the technology.
SE: What else?
Patton: By the way, there’s multi-sourcing. We have a fab coming up in Chengdu, China. Also, we know China will be a big market for FD-SOI. That’s been pretty clear from the conversions we’ve had with customers in China. So, we will have two big factories for FD-SOI—Dresden and Chengdu.
SE: Some analysts say you need more IC design resources to make chips around FD-SOI, as compared to bulk CMOS. Is that the case?
Patton: That’s some of the FUD (fear, uncertainty and doubt) spread by our competitors. We have programs to help teach our customers how to use back-bias. A number of them are starting out without back-bias. They get that under their belt, and then they can take the product to the next level by using back-bias. Some of our ecosystem partners are putting the tools in place, so that it’s fairly easy to design with back-bias. You do have to think about how you want to architect the system. That’s where they provide their value in terms of differentiation and figuring out how they want to leverage this thing called body-bias at a circuit, block or chip level.
SE: Why do designers need back-bias for FD-SOI?
Patton: You can apply that in a couple different ways. You can tune the voltage on a given chip. So you can tighten up the distributions of the product. Or you can take a block and throttle it up or down. I have an example in some of the presentations I give of a chip, where you have a block which is always on. And it’s a processor that is monitoring what’s going on in the environment. And you use the ultra-low leakage devices in that area. And the rest of it has the high-performance devices, but they are throttled down by body-bias. And so once you detect whatever is going on in the room, you power up the part that you care about. In addition, you have RF integrated on the chip. You send the signal, finish the communications, shut that part back down, and you go back into sleep mode. That’s really optimized for battery-powered applications. The part that’s always on uses ultra-low leakage devices. The other parts use body-bias to turn it on or off.
![[IMG]](https://semiengineering.com/wp-content/uploads/2017/06/fig.3.png)
Fig. 3: What is body-bias?
SE: What about 12nm FD-SOI? Why not offer that at 10nm?
Patton: It’s still planar and we have to go to double patterning. 10nm is a repeat of history on 20nm. 10nm takes things just to the point where you need triple patterning. And so we backed off a little in scaling with a big mask cost reduction. We don’t invoke as many double- or triple-patterning levels. So if you compare it to 10nm, 12nm FD-SOI is 40% less masks. And our 22nm is about 40% less masks than 14nm/16nm.
SE: There is also a perception that FD-SOI suffers from higher substrate costs. Any thoughts?
Patton: That’s only part of the equation. When you get a big mask cost savings, you are saving etch steps, deposition steps and others. It compensates for it.
SE: Let’s move to chip scaling. Is the industry keeping up with scaling or Moore’s Law?
Patton: It used to be simple. The industry was scaling 50% and would add 10% or 15% complexity for a 30% to 35% die cost improvement. But now you are adding 25% complexity. Let’s just pick that as a number. Now, you are only getting a 20% die cost improvement. That’s not quite as exciting for somebody doing design, especially if you look at the curves on design costs. Design costs have been going up at an exponential rate, so people have to spend more to design in this new technology.
SE: What about GlobalFoundries’ 7nm technology?
Patton: Our 7nm is scaled, versus 14nm, about 0.37x. We also know there are more masks than 14nm. At the end of the day, when you take the shrinkage and the complexity increase, we are giving customers a good die cost improvement for the investment they are going to make in the design.
![[IMG]](https://semiengineering.com/wp-content/uploads/2017/06/Fig4.png)
Fig. 4: Key innovations for 7nm. Source: GlobalFoundries
SE: GlobalFoundries decided to skip 10nm and move to 7nm. Why?
Patton: The scaling factor for 10nm is pretty modest. It’s more of a half node. All the things we’ve heard from customers is the performance improvement for 10nm is pretty marginal over the previous node in 16nm/14nm. So for 7nm, if you look at scaling and cost, it’s hitting that cost target of 30% to 35% die cost improvement.
SE: What are the big challenges for 7nm?
Patton: Clearly, the complexity is right up there. You are talking about something in the mid-80s for mask count, which is pretty amazing. The middle-of-line is also a key challenging area. Getting to the performance target is the third key challenge.
SE: For 7nm, GlobalFoundries said it would initially use 193nm immersion and multiple patterning, and not EUV. Is that still the case?
Patton: Yes, definitely. We have a number of products taping out next year, including the first one in the early part of next year. And EUV is not ready on that time frame. We do have EUV tools coming into Malta. We want to be prepared for the transition because it clearly offers advantages. We have two EUV tools coming in next year, and then we will have another two tools coming in the year after. So we will be well outfitted with EUV tooling. We have our EUV tool, of course, in Albany, which we are using with IBM for development. For manufacturing we will have EUV capability in place. And then we will transition customers and products over to that when it’s ready. It will give us a cycle time and a defect density improvement. And we’ll use it for a shrink on 7nm.
SE: So you plan to insert EUV at 7nm at some point?
Patton: We will launch 7nm with immersion. We will make sure our ground rules are compatible in order to migrate levels to EUV. And then, we’ll look at a shrink on that at the right time.
SE: What about the fins at 7nm? Do you need to make them taller to boost the drive currents?
Patton: We’ve gone a bit taller with the fins. There are some disadvantages of going to taller fins, as well. The fin shape is probably the most critical one. Getting the fin profile shape is critical. Also, getting that junction isolation is key. Your fin is isolated, but if you get too much overlap to the source-drain, it adds a lot of capacitance. This slows down the transistor.
SE: Is GlobalFoundries co-developing 7nm technology with Samsung?
Patton: We are doing it completely on our own. We had the collaboration on 14nm. We still partner with them on what I’d call pathfinding in Albany. As part of the deal with IBM, Albany used to be an all-joint-development alliance. Then it was spilt into two parts. Half of the facility continues to do the joint development work, which IBM leads. Think of that as pathfinding for 5nm and beyond. And the other half is a proprietary IBM-GlobalFoundries corridor, which is specifically focused on accelerating things into Malta. Those could be performance elements for 7nm and 7nm plus. In fact, I would envision we’ll have a bunch of performance kickers at 7nm. This will be a long node.
SE: So the finFET will last at least until 7nm. What about 5nm?
Patton: We have work going on that. We have work in new device structures like gate-all-around in Albany. Some think that you can go to 3nm with finFETs. I am a bit skeptical on that topic. We will need some new device structures before then.
MARK LAPEDUS
Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation.
SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI in R&D. Why develop both finFETs and FD-SOI?
Patton: We are providing our customers with technology that’s really optimized for their applications. We are not trying to fit everybody from high-end servers to battery-powered devices into one technology flavor.
SE: There is some confusion where FD-SOI and finFETs compete in the market. Can you elaborate?
Patton: I am a big fan of finFETs. I spend a lot of my time on 7nm. We are trying to get that ready for customer tape-outs early next year. It’s a great technology if you are used on performance. If you are making large chips and you have a lot of wire capacitance, you love the drive current of a finFET device. But if you are making smaller chips, where the gate capacitance is a bigger issue, then the finFET has a little bit of a disadvantage. Also, it’s a much more complex process. Not everybody is making a million wafers for their products. It’s a more expensive process. And it has more complexity with double-, triple- and quadruple- pattering, as well as the complexities with RF and analog design in a finFET device.
SE: What about FD-SOI?
Patton: FD-SOI is really a technology optimized for the low-cost IoT, battery-powered, low-end mobile and automotive applications.
SE: Do you push one technology over another?
Patton: We’re agnostic. We’re not telling customers that you have to do finFETs or FD-SOI. We want customers to use the technology that fits their application.
SE: Who are the early adopters for 22nm FD-SOI?
Patton: Automotive is definitely one of the strong ones. The camera space is another, and some of the battery-powered IoT.
SE: What’s happening in automotive?
Patton: Certain applications in automotive are better optimized for FD-SOI like radar. Other applications may use finFETs. So we are actually going through automotive qualification in our Malta fab for 14nm. Again, the auto makers can choose.
SE: GlobalFoundries has announced 22nm FD-SOI with plans to add more capabilities to the technology, right?
Patton: The base technology is done. The base IP development is done. And now, we are working on the extensions. We believe one of the killer applications for this is to be able to do a single-chip solution for the IoT space. That’s RF and everything.
SE: What else are you doing with FD-SOI?
Patton: There’s embedded memory. We have MRAM, which we will bring in. And, of course, we have 12nm work going on.
SE: IP is key for FD-SOI, right?
Patton: The yields are basically at 28nm yields. Performance is above our targets. It’s fully qualified. Now the focus is continuing to build up the IP ecosystem. We have the foundation and application IP in place.
SE: 22nm is one of the new battlegrounds in the foundry business. First, GlobalFoundries rolled out 22nm FD-SOI. Then, TSMC introduced a 22nm bulk process. And Intel introduced a new version of its 22nm finFET technology. What’s happening here? And how does 22nm FD-SOI stack up against the other technologies?
Patton: All of a sudden, 22nm has become a big battleground. Certainly, if you are looking at anything with RF requirements, I wouldn’t even put finFET in the game, because finFETs don’t have the same RF capabilities that a planar device has. So it becomes bulk versus FD-SOI. And FD-SOI is really optimized for this low-power space. With bulk, you don’t have the ability to do body-bias.
Fig. 1: Bulk CMOS vs FD-SOI. Source: GlobalFoundries
Fig. 2: 7nm finFET. Source: GlobalFoundries
SE: There is a perception that only a few customers have adopted FD-SOI. What are the challenges of getting more adoption for FD-SOI?
Patton: We’ve worked with lead customers on FD-SOI and they now understand the issues. First, there was the history or concerns about execution. We are well past that.
Commentary: This is important...with there Dresden news of FDX a PILLAR with China Chengdu center of excellence.....there are huge news items to show how well FDX is rolling along now
People understand 22nm. It’s solid technology and it’s yielding very well. We’ve executed what we’ve planned. We knew IP was going to be critical, because FD-SOI is new and different for people. So we’ve been investing from the beginning on the IP ecosystem. Our initial partner was Invecas to help build up the foundational IP. Since then, we’ve made a big increase and investment in all of the IP around the technology.
SE: What else?
Patton: By the way, there’s multi-sourcing. We have a fab coming up in Chengdu, China. Also, we know China will be a big market for FD-SOI. That’s been pretty clear from the conversions we’ve had with customers in China. So, we will have two big factories for FD-SOI—Dresden and Chengdu.
SE: Some analysts say you need more IC design resources to make chips around FD-SOI, as compared to bulk CMOS. Is that the case?
Patton: That’s some of the FUD (fear, uncertainty and doubt) spread by our competitors. We have programs to help teach our customers how to use back-bias. A number of them are starting out without back-bias. They get that under their belt, and then they can take the product to the next level by using back-bias. Some of our ecosystem partners are putting the tools in place, so that it’s fairly easy to design with back-bias. You do have to think about how you want to architect the system. That’s where they provide their value in terms of differentiation and figuring out how they want to leverage this thing called body-bias at a circuit, block or chip level.
SE: Why do designers need back-bias for FD-SOI?
Patton: You can apply that in a couple different ways. You can tune the voltage on a given chip. So you can tighten up the distributions of the product. Or you can take a block and throttle it up or down. I have an example in some of the presentations I give of a chip, where you have a block which is always on. And it’s a processor that is monitoring what’s going on in the environment. And you use the ultra-low leakage devices in that area. And the rest of it has the high-performance devices, but they are throttled down by body-bias. And so once you detect whatever is going on in the room, you power up the part that you care about. In addition, you have RF integrated on the chip. You send the signal, finish the communications, shut that part back down, and you go back into sleep mode. That’s really optimized for battery-powered applications. The part that’s always on uses ultra-low leakage devices. The other parts use body-bias to turn it on or off.
Fig. 3: What is body-bias?
SE: What about 12nm FD-SOI? Why not offer that at 10nm?
Patton: It’s still planar and we have to go to double patterning. 10nm is a repeat of history on 20nm. 10nm takes things just to the point where you need triple patterning. And so we backed off a little in scaling with a big mask cost reduction. We don’t invoke as many double- or triple-patterning levels. So if you compare it to 10nm, 12nm FD-SOI is 40% less masks. And our 22nm is about 40% less masks than 14nm/16nm.
SE: There is also a perception that FD-SOI suffers from higher substrate costs. Any thoughts?
Patton: That’s only part of the equation. When you get a big mask cost savings, you are saving etch steps, deposition steps and others. It compensates for it.
SE: Let’s move to chip scaling. Is the industry keeping up with scaling or Moore’s Law?
Patton: It used to be simple. The industry was scaling 50% and would add 10% or 15% complexity for a 30% to 35% die cost improvement. But now you are adding 25% complexity. Let’s just pick that as a number. Now, you are only getting a 20% die cost improvement. That’s not quite as exciting for somebody doing design, especially if you look at the curves on design costs. Design costs have been going up at an exponential rate, so people have to spend more to design in this new technology.
SE: What about GlobalFoundries’ 7nm technology?
Patton: Our 7nm is scaled, versus 14nm, about 0.37x. We also know there are more masks than 14nm. At the end of the day, when you take the shrinkage and the complexity increase, we are giving customers a good die cost improvement for the investment they are going to make in the design.
Fig. 4: Key innovations for 7nm. Source: GlobalFoundries
SE: GlobalFoundries decided to skip 10nm and move to 7nm. Why?
Patton: The scaling factor for 10nm is pretty modest. It’s more of a half node. All the things we’ve heard from customers is the performance improvement for 10nm is pretty marginal over the previous node in 16nm/14nm. So for 7nm, if you look at scaling and cost, it’s hitting that cost target of 30% to 35% die cost improvement.
SE: What are the big challenges for 7nm?
Patton: Clearly, the complexity is right up there. You are talking about something in the mid-80s for mask count, which is pretty amazing. The middle-of-line is also a key challenging area. Getting to the performance target is the third key challenge.
SE: For 7nm, GlobalFoundries said it would initially use 193nm immersion and multiple patterning, and not EUV. Is that still the case?
Patton: Yes, definitely. We have a number of products taping out next year, including the first one in the early part of next year. And EUV is not ready on that time frame. We do have EUV tools coming into Malta. We want to be prepared for the transition because it clearly offers advantages. We have two EUV tools coming in next year, and then we will have another two tools coming in the year after. So we will be well outfitted with EUV tooling. We have our EUV tool, of course, in Albany, which we are using with IBM for development. For manufacturing we will have EUV capability in place. And then we will transition customers and products over to that when it’s ready. It will give us a cycle time and a defect density improvement. And we’ll use it for a shrink on 7nm.
SE: So you plan to insert EUV at 7nm at some point?
Patton: We will launch 7nm with immersion. We will make sure our ground rules are compatible in order to migrate levels to EUV. And then, we’ll look at a shrink on that at the right time.
SE: What about the fins at 7nm? Do you need to make them taller to boost the drive currents?
Patton: We’ve gone a bit taller with the fins. There are some disadvantages of going to taller fins, as well. The fin shape is probably the most critical one. Getting the fin profile shape is critical. Also, getting that junction isolation is key. Your fin is isolated, but if you get too much overlap to the source-drain, it adds a lot of capacitance. This slows down the transistor.
SE: Is GlobalFoundries co-developing 7nm technology with Samsung?
Patton: We are doing it completely on our own. We had the collaboration on 14nm. We still partner with them on what I’d call pathfinding in Albany. As part of the deal with IBM, Albany used to be an all-joint-development alliance. Then it was spilt into two parts. Half of the facility continues to do the joint development work, which IBM leads. Think of that as pathfinding for 5nm and beyond. And the other half is a proprietary IBM-GlobalFoundries corridor, which is specifically focused on accelerating things into Malta. Those could be performance elements for 7nm and 7nm plus. In fact, I would envision we’ll have a bunch of performance kickers at 7nm. This will be a long node.
SE: So the finFET will last at least until 7nm. What about 5nm?
Patton: We have work going on that. We have work in new device structures like gate-all-around in Albany. Some think that you can go to 3nm with finFETs. I am a bit skeptical on that topic. We will need some new device structures before then.
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