http://www.eejournal.com/archives/articles/20141014-hipp/
A nice read, its the adjacent possible for QUIK and its SoC ambitions ( ARM core )
October 14, 2014
New Chips are HIPP
A Modest Proposal for a New Name
It’s time to speak up for the silent, to give a voice to the voiceless, to defend the downtrodden. Today is the day for action - for the engineering community to unite and right a wrong. We need to come to the aid of a technology in need, to give a name to the nameless. History is watching and will judge us by how we handle this epic dilemma.
I was giving a talk at an FPGA-related technology event recently, and the discussions in the room turned to the new category of devices that combine conventional processors with FPGA fabric on the same chip (or in the same package). These devices, like Xilinx Zynq, Altera SoC FPGAs, and others truly represent a new category of chips. While putting an FPGA next to a conventional processor is nothing new, there are major advantages to combining them into a single device that brings compelling new capabilities to the table.
“I wish somebody would name them!”
One of the engineers attending the event offered that request, and it was quickly reinforced by other attendees standing around. They’ve been called just “FPGAs,” “SoCs,” and a few other things, but none of the names adequately describe these new devices or distinguishes them from other chips that don’t have the same capabilities. The consensus was that these chips constitute a completely separate and important category, and they need a name.
If either Xilinx or Altera proposed a name, of course, the other one would steer as far from that label as possible. Initially, Xilinx was calling them “Extensible Processing Platforms” or “EPPs,” but the company dropped that label like a hot potato right after they started using it. Compounding the problem, Xilinx and Altera, being two highly competitive companies, seem to have a difference in strategy in the marketing positioning of these devices.
Xilinx does not have the “FPGA” label associated with Zynq at all. It appears that they are reaching for the large, non-FPGA-designer audience with these chips. That audience contains a large number of software-oriented engineers, who are accustomed to designing conventional “SoCs” into their systems (devices with processors and peripherals all on one chip produced by companies like Freescale). That audience might well be put off by the “FPGA” label, as there is a great deal of fear in the non-FPGA community of the complexity of FPGA design and FPGA tools.
Altera, on the other hand, is flying the FPGA banner proudly. Altera refers to all of their devices with embedded processing subsystems as “SoC FPGAs.” While that may be a perfectly good label, it has a couple of drawbacks. And, the first of those, of course, is Xilinx.
Altera and Xilinx are not the only players in this game. FPGAs with some kind of processors on them - or processors with FPGA fabric in them - or “those thingies that have both CPUs or MCUs and LUTs” have been around for quite a while. Actel introduced a line of flash-based, non-volatile FPGAs with ARM-based processors on them years ago. And, if you include FPGAs where conventional processor architectures can be implemented in the LUT fabric itself - Lattice also joins the list.
But, if the companies selling these FPGA/CPU/Memory/IO/DSP chips aren’t going to name them, who is? There’s no IEEE working group deployed to come up with a suitable moniker. The ACM doesn’t have a “name that chip” function in their charter. There hasn’t been a cutesy label like “phablet” that has caught on in the social media sphere.
Let’s do this thing!
We’re going to walk through some logic here and wind our way to proposing a name. Then, we want to hear from you - the worldwide audience of people-who-might-use-these-chips. Finally, we want to see if the companies that make the devices care to join the fun. Then, who knows? We might even try to put up a wikipedia page.
In our humble opinion, these chips need a name because they represent a new kind of capability - a heterogeneous computing platform with the capability of partitioning functionality between software and hardware implementations for optimal efficiency and performance. Because they typically include conventional processors like single- or dual-core ARMs, they offer highly capable conventional software-programmable processing capability. They also sport a robust set of peripherals like interfaces, memory controllers, etc., all interconnected by a bus or switch fabric such as AMBA/AXI, and at least some amount of on-chip memory.
But what we’ve described already is commonly referred to as an “SoC” (system on chip). Now, there are serious problems with the SoC label itself, and we’ll get into those in a minute, but the chips we’re naming definitely have everything that’s on a typical SoC, and a lot more besides. The “a lot more” consists of generous quantities of FPGA LUT fabric (which can implement additional peripherals, bridging logic, or computational accelerators), DSP blocks (which are very handy in making high-performance, low-power parallelized hardware accelerators for complex math algorithms), and high-speed interfaces.
With all of those “a lot more” features, we’re talking about something significantly more than what we call an “SoC.” But, with all the processor-related stuff, it’s also quite a bit more and much different from what we typically call an “FPGA.” It’s obvious at this point how Altera arrived at the “SoC FPGA.” But, because of the primary use case, processing, these devices are a lot more “SoC” than “FPGA.”
These chips also offer a lot more than what you get when you park an FPGA next to an SoC on your circuit board. In these devices, the processing subsystem and the FPGA are connected by a massive-bandwidth connection. FPGAs have enormous routing resources, and those resources provide full access to the processor, switch fabric, and shared on-chip memory. Additionally, since that large bandwidth doesn’t require going back and forth between two separate chips (as it would with something like a PCIe interface), the power required to cross the processor/FPGA divide is significantly lower, the speed is much higher, and the latency (due to not having to serialize/deserialize the data) is much lower. That means we can do a lot of cool new stuff - particularly in the area of accelerating algorithms running on the processors.
Using these devices for algorithm acceleration has several advantages. A parallelized, hardware implementation of a critical algorithm in FPGA fabric is of course much faster than the same algorithm implemented in software, but, more importantly, it uses much less power. For applications like embedded vision, that increased performance with decreased power requirement can make the critical difference between success and failure in our implementation. The ability to make the connections between the accelerator, the memory, and the processor work with low power and low latency makes this architecture that much more attractive.
A machine that lets us partition algorithms into software and hardware functions that work together has historically been called either a “reconfigurable computer” or a “heterogeneous computer.” So, for our proposed name, we probably want “reconfigurable” or “heterogeneous” represented in the name. If it’s an acronym, that means we could have an “H” or an “R” in the mix.
Because we’re talking about computation here as the primary function of the device, we need something in the name to reflect that. We could either use a “C” for “computer” or a “P” for “processor.” So, that gives us all the permutations of H/R and C/P as options. But, it’s also important that our device is “integrated” versus separate chips for processor and FPGA. That means there should probably be an “I” in there as well. Finally, our devices are not just “processors.” They are capable of integrating a large number of functions besides just processing. They are, in fact, platforms, so that gives us another “P.”
So here we are with H/R, C/P, I, and P. We’d also like for the result to be pronounceable, and for the acronym to avoid conflict with other acronyms in the technology arena. IRCP (for “Integrated Reconfigurable Computing Platform”) runs the risk of confusion with “Internet Relay Chat Protocol,” for example. It would also be nice if the resulting pronunciation had a positive connotation. “Integrated Reconfigurable Processing Platform” or “IRPP” seemed to fail that test.
With all that in mind, we went through a range of options, and came up with “HIPP” for “Heterogeneous Integrated Processing Platform.” As you can see, there were numerous other choices, but they all seemed less cool and not nearly as … um … “hip” as this one. What do you think? Would you design your system around a HIPP chip?
