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   As things move forward and QUIK unveils the wearable Eos platform. I wanted to read this again…
   
   
   
   
   
   
   August 4, 2015
   
   SoC Everywhere
   Is the Future All One Thing?
   by Kevin Morris
   
   Sometimes, while wrapped up in the day-to-day minutia of technology trends, we can lose sight of the big, slow movements. Underneath the fast-paced, frenetic world of next-node Moore’s Law chaos are some giant trendline tectonic plates - slowly sliding, shifting along fault lines that are barely visible in our normal tech lives.
   
   Let’s fire up our future-facing seismometers and see what electronic bastions are poised to slide off into the ocean when the next “big one” hits.
   
   For the past thirty years, there has been extreme diversity in chips and in chip makers. We have processor companies making processors, of course; memory companies, microcontroller companies, FPGA companies, analog companies, RF companies, interface companies - every specialized type of chip hosts a mini-market of semiconductor specialists, competing for points of market share in their own little tightly-walled technology arena.
   
   Intel squares off against the likes of AMD. Xilinx and Altera feud like the Hatfields and McCoys, Linear Technology, Texas Instruments, and ADI spar with each other in the analog world. Samsung, Micron, and others dominate the memory game. Each of these contests exists almost in a bubble, oblivious to the gyrations in the adjoining market spaces.
   
   Deep down below the surface, however, Moore’s Law pushes the forces of integration and consolidation forward, gradually stressing the landscape above. The poster child for this movement is the never-more-appropriately-named “System on Chip” (SoC). We started calling chips SoCs before we had any right to. As soon as we could put a processor and - just about anything else - on a single chip, we called it a “System.”
   
   Now, however, SoCs are starting to actually deserve the label. SoCs from Xilinx and Altera can have numerous 64-bit applications processors, graphics processors, MPUs, memory, FPGA fabric, non-volatile storage, high-speed IO, and even a little analog - all on one device. 3D packaging techniques promise to make this type of integration go even farther - with the potential to put silicon from completely different processes on the same interposer. It’s not inconceivable that we’d have RF, analog, heterogeneous processors, digital logic, memory, non-volatile storage, high-speed IO, and even MEMS - all in one package or on one silicon interposer.
   
   If you look at the various specialized silicon vendors, you’ll start to notice that - at some level - almost all of them are now producing SoCs. We may be heading for a time when there is only an “SoC” market, rather than a fragmented collection of specialized silicon vendors. What we might see, then, is a re-partitioning of the market - into the application areas served, rather than the type of chip architecture being delivered. Automotive systems engineers would get their SoCs from one vendor, telecommunications and networking from another, and cloud computing from yet another. While the silicon will still be differentiated, the primary way that companies will need to compete will be on the things surrounding the silicon - support, reference designs, development boards, hardware and software development tools, IP, and so forth.
   
   If we look at the trajectories of the various elements, we can divine even more. For example, random logic is becoming essentially free. You can put multiple applications processors, MCUs, graphics engines, DSP processors, and other types of specialized processing elements on your chip for virtually no incremental cost in silicon area. So - why wouldn’t everybody throw them in? Even FPGA fabric is headed down the curve toward zero cost in silicon area. You can put more FPGA fabric than most applications could use on a chip for very little incremental cost.
   
   Memory is a different story. Today’s applications have a voracious appetite for memory, and it looks like it will be a long time (or never) before “more memory than you will probably use” will be small and cheap enough to throw onto every chip. As Moore’s Law progresses, and we put as much of the non-memory gunk on our chip as anyone could want, we’ll probably use the rest of the space for memory.
   
   By the same token, IO does not follow the curve of Moore’s Law. The amount we spend to route a single signal from our chip to a board hasn’t dropped all that much, and our appetite for more IO pins has grown rapidly, although not nearly at a Moore’s Law pace (thank goodness, or we’d have devices with a billion pins by now). The pace of increased integration helps offset the pin glut, however, as the more signals we can route between connected blocks inside our chip or module, the fewer we have to bring out to the real world on our board. 
   
   Following these three trends, we can visualize ending up in a world where processing and logic are basically free and ubiquitous, analog is present in sufficient quantities on most devices, memory is a commodity, and IO pins are at a premium. Even using the rules of that world, we could end up with far fewer different chips than we have today. A small number of different SoCs could be adapted to solve a huge variety of problems in a wide range of applications. The people buying those SoCs would be much less interested in the hardware and its capabilities than in the software, support, and application-readiness of the ecosystem surrounding the SOCs.
   
   If the world of chips may become less diverse and specialized, the world of applications continues to expand. That means that opportunities for “silicon” companies could be much more related to their ability to understand and serve particular applications than to their ability to build differentiated chips. Look for silicon vendors to spend more time understanding your actual challenges and less time bragging about how their max DSP performance is umpty-gazillion teraFLOPs and their power consumption is “3x lower” than their nearest competitor.
   
   In this world, software IP will also take on a very important role. If the chips are not particularly differentiated, and the development tools are fairly similar from different vendors, the way to your heart will be with software stacks and reference designs that do a lot of your grunt work for you. In that world, you may just have to grab the dev kit and start work right away on your magic secret software sauce. The rest may already be done.
   
   
   So this was written before we had reading material on Eos, but it fits very, very well into this essay.
   
   1.Its an SoC, not a fusion module ( INVN so far).
   
   2. Look for silicon vendors to spend more time understanding your actual challenges and less time bragging about how their max DSP performance is
   
   software IP will also take on a very important role.umpty-gazillion teraFLOPs and their power consumption is “3x lower” than their nearest competitor.
   
   
   
   Makes the move to talented algo chefs at QUIK so important. Many of the MCU folks will have a weakness here.
   
   
   
   Use this essay and the material we already have, with more material and news items to read yet this yr.
   Consider a mind shift soon, that QUIK IS not behind, leapfrogged, but just the opposite…
   
   they have a SoC, they have software IP, if its ubiquitous they will hard code a new engine in the roadmap with no risk to its acceptance ( it ubiquitous)
   
   Subjective probabilities ( Bayesian analysis) of success are shifting.