The rising performance of MCUs
Generally, though, there is a trend for more performance at the edge, so the challenge is to bring 8-bit power efficiency levels to bigger architectures. To the delight of chipmakers, the IoT is re-placing one chip with several in many instances – for instance, an Cortex-M0+ sensor hub coupled with a Cortex-M4 or –M7 doing the apps processing.
Generally, though, there is a trend for more performance at the edge, so the challenge is to bring 8-bit power efficiency levels to bigger architectures. To the delight of chipmakers, the IoT is re-placing one chip with several in many instances – for instance, an Cortex-M0+ sensor hub coupled with a Cortex-M4 or –M7 doing the apps processing.
My commentary
- note the 2 ARM core chips in the underlined text…M0+ for a sensor hub, next tier up they want an M4 or 7 for higher level fusion. QUIK is going to do the same thing…only much better.
Why much better you ask?The M0+ has NO math unit for Kalmans of sesnor fusion. while the smallest of the ARM cores the power savings over the M4 are very minimal, I looked it up, and don’t have the exact numbers, its a LOT less than you would think, ie GOOD for QUIK, as they will put the huge power saving of the FFE with its math unit in front of the M4 or M7, ( will they do both one day? ;-)). In the above they use the phrase…re-placing one chip with several
QUIK will not only do it better, but it will also be a SoC. one chip, less real estate used up etc.
What will the others do?
They will just put those 2 cores together to make an SoC. The M0+ with an M4/M7. Little and big.
This is where the other part of the name of this blog comes in...Steven Johnson's "adjacent possible". What will the others do?
They will just put those 2 cores together to make an SoC. The M0+ with an M4/M7. Little and big. It the bits and pieces that they have so they will stick them together...like this one from NXP archives
NXP’s New Dual-Core Cortex-M4 and M0 MCU Redefines Digital Signal Control
November 01, 2010
LPC4000 family’s unique configurable peripheral subsystem allows developers to tailor MCU and DSP solutions
Eindhoven, Netherlands and San Jose, California, November 1, 2010 – NXP Semiconductors N.V. (Nasdaq: NXPI) today announced the LPC4000 family, the world’s first asymmetrical dual-core digital signal controller architecture featuring ARM® Cortex™-M4 and Cortex-M0 processors. The LPC4000 brings the advantage of developing DSP and MCU applications within a single architecture and development environment. With this dual-core architecture and a set of unique configurable peripherals, the LPC4000 enables customers to develop a wide range of applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio. NXP will be showcasing the LPC4000 simultaneously at electronica 2010 in Munich, Germany from November 9 to 12, and at ARM TechCon, Santa Clara, California, from November 9 to 11.
“The LPC4000 is not just another Cortex-M4. We’re introducing multi-core processing to microcontroller and DSP applications,” said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. “Equally important are the configurable peripherals that enable LPC4000 users to reduce the need for external ASIC functionality.”
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QUIK bits and pieces will be different...the next add on to the S2 + and M4/7. QUIK has the bits and pieces to make the VERY BEST SoC there will be.
Audio processing may be big for wearables, audience uses DSPs, the M7 will be able to do this also?
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