On this snip...
Certainly QUIK at this point isn't involved with any sales effort or engagement.
There are reasons and snips of text that support engagements. Myself
since it takes a fair bit of work and $$ to do each node- There has to be engagements for each one we have...60,40,.
I used QUIKs snips on 55nm. We would NOT spend the precious time or $$ for 55nm unless a silicon maker WANTs it. They asked for it and we will read of it- maybe fairly soon?
The road shows with SMIC and soon GLo FOs road show are exactly sales efforts with SMIC AND Global Fo...
So for me there ARE real sales efforts, there are engagements.
Perhaps most important, we have a local office, local people, on the ground there, that is VERY important in China.....to support all along the way.....also IP PROTECTION.
Its so easy for me to compare A to B
Would you rather have been Lattice and dance at the acquisition ball, or
create eFPGA and the margins?
This is why we are part owners of this business. They have changed the company for the better. PMCW was spot on to point to the difference.
If there is value in FPGA IP...what has this eFPGA effort done for the value of our IP?
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Want to reread this Jan QUIK job listing....
Here is the job again
Senior ASIC Integration Applications Engineer
Taiwan
Worker Category :Full Time Regular
Job Class
Overview
QuickLogic’s ArcticPro eFPGA is being licensed by several Tier-1 customers for integration into their SoCs.
Commentary: we had several Tier 1 semi engagements back in Jan.? My own conclusion was that this is NOT what we know, i.e. SMIC and GLo Fo- this refers to makers of SoCs; design houses not the Fabs themselves. Also that the reason we got SMIC and GLoFo was that customers were asking for it....and we were ready to give them what they wanted?
The Sr Application Engineer (AE) will be responsible for supporting QuickLogic’s licensees during Technology porting, customer evaluations, and SoC integration. Strong leadership, problem solving ability, effective communications and positive customer service skills are required.
Key responsibilities include:
- Provide direct customer/partner support during design porting, eFPGA integration into customer SoC.
- Providing front line support for handling customer issues, including replication of customers’ bugs, debugging, reporting and acceptance.
- Create competitive analysis, technical papers and technical collateral
Education, Knowledge & Skills Profile
BS/MS Electronics Engineering with 7+ year experience in digital design area.
5+ years of experience on RTL coding/development in SOC and/or ASIC environment and strong background in logic design skills.
Additional experience in/with:
- Whole Chip integration, Flash/Memory/Analog IP integration, AMBA bus, SPI, I2C and/or other similar peripherals design
- Synthesis using Design Compiler and/or similar tool
- Static Timing Analysis using Primetime and/or similar tool
- Power domain partition and implementation.
- Working with Backend team and knowledge of Backend flow
- DFT/SCAN/Production methodology and/or tools
- RTL Verification and Silicon Validation
- Hands on Perl Scripting or other scripting language
- Excellent communication skills, both written and verbal
- Prior experience working with in multi-site, multi-cultural teams.\
- Big plus FPGA design experience
- Basic understanding of custom design flow
- Good communication skills in English and Mandarin
- This position will require ability to travel internationally without restrictions.
, Taiwan location with a focus on the licensees. The only one I have found with HQ there is Mediatek.
Yes we expect some others as this person needs to travel.
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