1. 
   

   Is RISC-V a risk to ARM $$.
   
   Will any future generations of chips stay with ARM or move to RISC-V? ( S4 even)
   
   will track along
   
   Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark
   By
   Tiernan Ray
   Updated Jan. 3, 2018 12:52 p.m. ET
   
   
   If you like semiconductors, you should really check out this “RISC-V” thing, according to a missive today from Gary Mobley of The Benchmark Company. 
   
   RISC-V, in case you don’t know, is the latest incarnation of the “reduced instruction set computing” architecture, devised by Professor David Patterson of U.C. Berkeleyabout 40 years ago. I interviewed Patterson about RISC-V last summer for Barron’s print magazine.
   
   
   
   
   
   The notion is that by making the “instruction-set architecture,” or ISA, of a chip more like open source, where it can be modified, it is possible to make chips that are tailored to a given need and therefore more efficient and less costly to produce. Some of these qualities are evident in the “Tensor Processing Unit,” or TPU, which Patterson helped devise for Alphabet’s (GOOGL) Google’s machine learning efforts.
   
   Mobley, who plans to hold a conference call about the topic on January 22nd, with the executive director of the RISC-V Foundation, Rick O’Connor, today offered up a summary of the non-profit organization and also the support its gaining by chip makers.
   
   He notes that hard drive and NAND flash chip maker Western Digital (WDC) recently gave its endorsement to RISC-V "as the company has pledged to transition its own consumption of processors to RISC-V."
   
   "Western Digital ships over one billion cores per year, and plans to double that number,” notes Mobley.
   
   
   "And if all goes according to plan, they will all be based on RISC-V, according to recent statement."
   
   Mobley also points out that graphics chip titan Nvidia (NVDA) "quietly revealed that it’s going to build its next-generation GPU microcontroller on the RISC-V ISA,” which I had also learned independently from Patterson and from a company founded by one of his graduate students, SiFive.
   
   Investors should pay attention, writes Mobley, because there could be “disruptive” effects upon traditional processors, which could ripple through the fortunes of many chip companies:
   
   Any investor interested in learning how adoption of RISC-V stands to disrupt the CISC and RISC processor domains, including discrete processors and/or processor IP (cores and architectures) embedded within simple MCUs as well as advanced ASICs. Additionally, RISC-V stands to disrupt R&D development roadmaps for merchant and captive SoC companies. For example, if Western Digital truly intends to adopt RISC-V in storage products, Marvell (MRVL; Buy; $30 PT) will need to reconsider usage of Arm cores. This could lower the upfront licensing and royalty costs for Marvell; however, it may require a revamping of Marvell’s storage controller design flow. Processor IP companies such as Arm Holdings, Synopsys (SNPS; Hold), Cadence Design (CDNS; Hold), Imagination Tech (NR) and even CEVA, Inc. (CEVA; Buy; $55 PT) could see an impact.
   
   
   Will track this along.
   On the surface... Tensor -TPU is quite an endorsement?
   
   Rick has said many makers want to get rid of MCUs.
   RISC-V, from the little reading material has this
   
   
   Another benefit of RISC-V is that it enables companies to develop a product that is tailored specifically to their workload, so they start with the RISC-V core and can add whatever it is they specifically need, saving both time and money.
   
   Western digital moving a billion cores- or 2.
   
   
   anybody in the business that can help in understanding please chime in.
   
   Tnks in advance.
   
   Brian Faith's sip of text...
   
   http://blog.quicklogic.com/corporat...a-new-platform-paradigm/#sthash.nXkjQxTZ.dpbs
   
   
   
   That high degree of flexibility really means that the SoC developer can create a platform rather than just a one-off product. And that fact has enormous consequences for the lifetime revenue and profitability of the SoC.
   
   Let’s look at this another way. We would go so far as to say that given the high costs and long development times associated with SoCs today, nearly every developer should be thinking in terms of platforms rather than products. An open source ISA, a leading edge but broadly available process node, and embedded FPGA technology are the perfect combination for creating a flexible SoC platform. Once you have such a platform available, you can create many products, each fairly easily, spun out through a combination of software (implemented on the open source ISA) and hardware (implemented in the eFPGA technology on chip) changes. Make the big investment in the platform, and small incremental investments in delivering highly market-tuned products to your end customers. In most cases that will be the way to extract the most value from your company’s intellectual property and market knowledge.
   
   Modifying mask sets to create new products is a time-consuming, expensive, and ultimately obsolete way of thinking. Welcome to the platform-based future that open source ISAs and eFPGA technology are helping to create.
   
   In this blog item, the first time I read it I thought...
   B Faith is more eloquent than anything else I have read by him.
   SO please consider that we let some time go by, but
   what he says would apple to any roadmap that QUIK
   has for future next generation devices?
   
   The S4 will be one of the first embodiments of this blog item?
   Will track along
   

   jfieb, 14 minutes agoEditDeleteReport

   #4Reply
2. 

   jfiebWell-Known Member

   
   

   RISC-V its a small world...
   
   devised by Professor David Patterson of U.C. Berkeleya
   
   
   
   a company founded by one of his graduate students, SiFive.
   
   
   
   
   SiFive Joins FDXcelerator™ Program to Bring RISC-V Core IP to GLOBALFOUNDRIES’ 22FDX® Process Technology
   
   
    Tweet  Share  Share 
   SAN MATEO, Calif. – Nov. 28, 2017 – SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX® process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.
   
   “As the RISC-V ecosystem continues to grow, SiFive’s leading CPU IP is seeing increased adoption. Our partnership with GF is going to enable an even larger pool of system designers to build on an industry-leading process platform,” said Naveed Sherwani, CEO, SiFive. “SiFive has led the RISC-V ecosystem from early on and we are excited to continue extending RISC-V into new market segments.”
   
   “As members of the RISC-V Foundation, we are excited to see more RISC-V IP offerings made available on our processes,” said Gregg Bartlett, senior vice president of CMOS business at GF. “SiFive’s wide range of cores makes them an ideal partner for our FDXcelerator program.”
   
   GF’s FDXcelerator Program brings together select partners to integrate their products or services into validated, plug-and-play design solutions, giving customers access to a broad set of quality offerings specific to 22FDX technology. The program’s open framework enables members to minimize development time and cost while simultaneously leveraging the inherent power and performance advantages of FDX technology.
   
   
   Glo Fo- 22FDX- cutting edge for many reasons.
   
   QUIK has early access to this IP
   
   It will have early access to the mRAM memory on the 22 FDX.
   
   
   It has early access to potentially disruptive RISC-V core.
   
   
   for its eFPGA or its own roadmap.
   
   They can ALL go together on one SoC.
   
   Its is doggone impressive?